三段式状态机设计

 1  //本例主要采用三段式状态机：在异步复位信号的控制下，一段式状态机进入IDLE
 2   //状态，q_sig4被复位，一旦sig1或者sig2有效，状态机进入WAIT状态，如果sig1和sig2同时有效，那么
 3  //状态机进入DONE状态，如果sig4还有效，那么q_sig4置位，同时状态机进入IDLE状态。
 4  
 5  module three_seg_fsm(clk,reset,sig1,sig2,sig3,q_sig4);
 6  //数据声明部分
 7  input clk,reset,sig1,sig2,sig3;
 8 
 9 output reg       q_sig4;
10 
11  reg [1:0]    current_state, next_state;
12 
13 //参数声明
14  parameter  IDLE       = 2‘b00;
15  parameter  WAIT       = 2‘b01;
16  parameter  DONE       = 2‘b10;
17 
18  //状态跳转程序设计
19 always @(posedge clk or posedge reset)
20  if(reset)
21       current_state <= IDLE;
22   else
23       current_state <= next_state;
24       
25  //状态跳转输出
26  always @(current_state or sig1 or sig2 or sig3)
27    begin
28        case(current_state)
29        IDLE: begin
30                               if(sig1 || sig2)
31                                    begin
32                                        next_state = WAIT;                                      
33                                    end
34                                   else
35                                       begin
36                                           next_state = IDLE;                                         
37                                     end
38                            end
39                    WAIT: begin
40                              if(sig2 && sig3)
41                                 begin
42                                      next_state = DONE;                                    
43                               end
44                            else
45                                 begin
46                                      next_state = WAIT;                                    
47                                end
48                           end       
49                                      
50                    DONE:begin
51                             if(sig3)
52                                 begin
53                                     next_state = IDLE;                                   
54                                 end
55                             else
56                                 begin
57                                     next_state = DONE;                                   
58                                 end
59                            end
60                     
61                  default: begin
62                               next_state = IDLE;                             
63                             end
64            endcase       
65    end
66    
67    //逻辑输出
68    always @(posedge clk or posedge reset)
69      if(reset)
70          q_sig4 <= 1‘b0;
71      else
72          begin
73              case(next_state)
74                  IDLE,
75                  WAIT: q_sig4 <= 1‘b0;
76                  DONE: q_sig4 <= 1‘b1;
77                  default: q_sig4 <= 1‘b0;
78            endcase
79          end
80          
81  endmodule