主要三个script:
mbist_run: call mbistarchitect tool
run.do:run bist flow bist setup => bist mode(bist gen / bist insert) =>bist integrate
mbist.do: config bist logic fsm (定义算法 定义修复逻辑 定义output )
mbist_run:
mbistarchitect ../netlist/top_name.v -rep -top top_module_name -logfile bist_log -insertion -dofile ../scripts/run.do -lverilog ../models/instance_name.v
run.do:
//1.setup mode(perform load library and load design object and arg configurate)
///1.1 load lib
load library ../models/instance.lib
///1.2 configuration
add clocks 0 clock
add new port bist_mode -dir in
add new port bist_done -dir out
add new port bist_fail -dir out
add pin sharing bist_clk clk
report clocks
report pin sharing
//2. bist mode (perform add new controller or add existing controller)
set system mode bist
report memory instances
add new controller u_top_bist -do ../scripts/mbist.do u_instance_name
report memory instances
add pin mapping bist_mode u_top_bist/test_h
add pin mapping bist_done u_top_bist/test_done
report pin mapping
//3. insert bist logic(perform the generation activity and the insertion activity)
insert bist logic
report controllers
save design -rep -inc rtl
//4.integration mode(perform add pattern translation and delet patterns)
set system mode int
add pattern translation -all
//5.about pattern
integrate pattern
report pattern translation
report controller description
//6.save and exit
save patterns mapped.v -rep -verilog
report concurrent group -all
exit
mbist.do:
reset state
add memory model instance_name -collar instance_name_collar
report mbist algorithms
set bist insertion -on
setup memory clock -test
setup memory clock -con
set design name controller -module controller_name
set file naming -bist bist_name.v
set file naming -con bist_name_con.v
set file naming -test bist_name_tb.v
set file naming -wgl bist_name_wgl.v
set file naming -ctdl bist_name_ctdf.ctdf
report design name
report pin name
run
report pin name
save bist -verilog -replace
report environment
exit -d
原文：http://www.cnblogs.com/chip/p/5146848.html