1. 38译码器

 1 library IEEE;
 2 use IEEE.STD_LOGIC_1164.ALL;
 3 use ieee.std_logic_signed.all;
 4 
 5 
 6 entity top is
 7 port (
 8         sel: in std_logic_vector (2 downto 0);
 9         y: out std_logic_vector(7 downto 0)
10 --    sel : in bit;
11 --    y : out bit
12     
13 );
14 end top;
15 
16 architecture Behavioral of top is
17 
18 begin
19 process (sel)
20 
21 begin
22 --if(sel=‘0‘) then y<=‘0‘;
23 --else y<=‘1‘;
24 --end if;
25     case sel is
26         when "000" => y<="00000001";
27         when "001" => y<="00000010";
28         when "010" => y<="00000100";
29         when "011"  => y<="00001000";
30         when "100"=> y<="00011000";
31         when "101" => y<="00100000";
32         
33         when "110" => y<="01000000";
34         when "111" => y<="10000000";
35         when others =>null;
36     end case;
37 end process;
38 end Behavioral;