编译时提示：
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410):
Pin "SCLK" is stuck at GND
Warning (13410): Pin "SYNCn" is stuck at
VCC
Warning (13410): Pin "Dout" is stuck at GND
三个输出端都被固定了在GND或者VCC，程序的本意并非如此，分析了一下部分底层模块代码：
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always@(negedge CLK or negedge RSTn) begin if(!RSTn) begin SCLK <= 1‘b0; end else begin SCLK <= ~SCLK; end end always@(posedge CLK or negedge RSTn) begin if(!RSTn) begin counter <= 8‘d0; end else begin counter <= counter + 1‘b1; if(counter == 8‘d62) counter <= 8‘d0; end end |
并没有发现错误，转而分析顶层
1 module MyDemo( 2 input CLK, 3 output SCLK, 4 output SYNCn, 5 output Dout 6 ); 7 wire BUSY; 8 reg RSTn = 1‘b1; 9 reg [20:0] counter; 10 reg [15:0] V_Data; 11 12 DAC8560 U1(.CLK(CLK),.V_Data(V_Data),.RSTn(RSTn),.SCLK(SCLK),.SYNCn(SYNCn),.Dout(Dout),.BUSY(BUSY)); 13 14 always@(posedge CLK) 15 begin 16 if(counter == 21‘d2000000) 17 begin 18 if(V_Data < 16‘d60000) 19 V_Data <= V_Data + 16‘d10000; 20 else 21 begin 22 V_Data <= 16‘d0; 23 end 24 end 25 else 26 begin 27 counter <= counter + 1‘b1; 28 end 29 end 30 endmodule
发现复位信号由于为了方便调试将RSTn置为1，将RSTn修改为实际引脚输入，编译后问题解决
1 module MyDemo( 2 input CLK, 3 output SCLK, 4 output SYNCn, 5 output Dout, 6 input RSTn 7 );
发现always所依赖的敏感信号如果为固定电平，很容易出现这种警告，具体原因待查。
Altera quartus II遇到的问题,布布扣,bubuko.com
原文：http://www.cnblogs.com/ARM-LINUX-WANG/p/3714227.html
