异步复位同步释放

module rst(
input clk,
input rst_n,
output reg rst_out
);

reg rst_R;

always@(posedge clk, negedge rst_n)
begin
    if(!rst_n)
        begin
            rst_R <= 1‘b0;
            rst_out <= 1‘b0;
        end
    else
        begin
            rst_R <= 1‘b1;
            rst_out <= rst_r;
        end
end
endmodule