lcd_1602

module lcd_pdf(
        clk,lcd_data,
        lcd_rw,lcd_rs,
        lcd_en,rst_n
);

input                        clk;
input                        rst_n;
output    reg    [7:0]    lcd_data;
output    reg            lcd_rw;  // wirte      L
output    reg            lcd_en; 
output    reg            lcd_rs;

//clock 分频
reg    [24:0]    cnt;
reg                clk_10;
always @(posedge clk or negedge rst_n)
    if(!rst_n)begin
        cnt <= 25‘d0;
        clk_10 <= 1‘b0;
    end
    else begin
        if(cnt == 5)begin
            clk_10 =~ clk_10;
            cnt <= cnt + 1‘b1;
        end
    end
        
//shixu
always @(posedge clk_10 or negedge rst_n)
    if(!rst_n)begin
        lcd_rw <= 1‘b0;
        lcd_en <= 1‘b0;
    end
    else begin
        case(cnt)
        100000:begin
                lcd_en <= 1‘b0;
                lcd_data <= 8‘h30;
                lcd_rw <= 1‘b0;
                lcd_rs <= 1‘b0;
            end
        100001:begin    
                lcd_en <= 1‘b1;
            end
        100010:begin
                lcd_en <= 1‘b0;
                lcd_data <= 8‘h0c;
                lcd_rw <= 1‘b0;
                lcd_rs <= 1‘b0;
            end
        100011:begin
                lcd_en <= 1‘b1;
            end
        100020:begin
                lcd_en <= 1‘b0;
                lcd_data <= 8‘h01;
                lcd_rw <= 1‘b0;
                lcd_rs <= 1‘b0;
            end
        100021:begin
                lcd_en <= 1‘b1;
            end
        100030:begin                
                lcd_en <= 1‘b0;
                lcd_data <= 8‘h80;
                lcd_rw <= 1‘b0;
                lcd_rs <= 1‘b0;
            end
        100031:begin
                lcd_en <= 1‘b1;
            end
        100040:begin
                lcd_en <= 1‘b0;
                lcd_data <= 8‘h30;//字符0
                lcd_rw <= 1‘b0;
                lcd_rs <= 1‘b1;
            end        
        100041:begin
                lcd_en <= 1‘b1;
            end
        default:lcd_en <= 1‘b0;
        endcase
    end
endmodule