port_cfg.h
witti:
#define PORT_CONFIG_PIN_E0_USAGE PORT_CONFIG_GPIO_OUT
magna:
#define PORT_CONFIG_PIN_E0_USAGE PORT_CONFIG_ALT1_OUT
in m_pot_bsw_cfg, Dlt_sci.c:
SIU.PCR[PORT_C_PIN_8].R = PORT_CONFIG_ALT1_OUT; /* SW_DEB_TX */
SIU.PCR[PORT_C_PIN_9].R = PORT_CONFIG_GPIO_IN; /* SW_DEB_RX */
Sci_IoHwAbMapping.cfg
PWM_CHANNEL_CFG ( E_BSW_PWO_MOTOR_B , BSWIF_PWM_MOTOR_B )
1. pwm.c
EMIOS_CHANNEL_PWM_MOTOR_B_UC initialization
Pwm_FrequencySweepRandom
2. emios_cfg.c
emios_cfg.h
+/* Require PMW_LOW = 8.0KHz */
+#define EMIOS_LATCH_PWM_FREQ_LOW 8000u
+/* Require PMW_HIGH = 12.0KHz */
+#define EMIOS_LATCH_PWM_FREQ_HIGH 12000u
+/* Require PMW_LOW = 8KHz --> 8MHz / 8KHz --> 1000 ticks */
+#define EMIOS_LATCH_PWM_FREQ_FACTOR_LOW (EMIOS_MODULE_FREQ/EMIOS_LATCH_PWM_FREQ_LOW)
+/* Require PMW_HIGH = 12KHz --> 8MHz / 12KHz --> 667 ticks */
+#define EMIOS_LATCH_PWM_FREQ_FACTOR_HIGH (EMIOS_MODULE_FREQ/EMIOS_LATCH_PWM_FREQ_HIGH)
原文：https://www.cnblogs.com/dannykong/p/10782376.html