chisel入门2--生成verilog

 1 import chisel3._
 2 
 3   class GCD extends Module {
 4     val io = IO(new Bundle {
 5       val a  = Input(UInt(32.W))
 6       val b  = Input(UInt(32.W))
 7       val e  = Input(Bool())
 8       val z  = Output(UInt(32.W))
 9       val v  = Output(Bool())
10     })
11     val x = Reg(UInt(32.W))
12     val y = Reg(UInt(32.W))
13     when (x > y) {
14       x := x -% y
15     }.otherwise {
16       y := y -% x
17     }
18     when (io.e) {
19       x := io.a
20       y := io.b
21     }
22     io.z := x
23     io.v := y === 0.U
24   }
25 
26 object GCDDriver extends App {
27   chisel3.Driver.execute(args, () => new GCD)
28 }

1 scalaVersion := "2.12.8"
2 
3 resolvers ++= Seq(
4   Resolver.sonatypeRepo("snapshots"),
5   Resolver.sonatypeRepo("releases")
6 )
7

　　scalacOptions ++= Seq ("-Xsource: 2.11 ")

8 libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.1.+"