1 `define width 8//用width代替数字8 2 reg [`width-1:0] a,b,c;//引用已定义宏名时需加上“`”
1 //`timescale 时间精度/时间单位 2 `timescale 1ns/10ps //表示时间单位1ns，时间精度10ps 3 module gate 4 ( 5 input a,b, 6 output out 7 ); 8 9 or #(4.23,5.67) A1(out,a,b); 10 11 endmodule 12 //上例中4.23延时值为4.2ns，5.67延时值为5.7ns
1 //若改为下例，则延时值分别为42ns,57ns 2 `timescale 1ns/10ps 3 module gate 4 ( 5 input a,b, 6 output out 7 ); 8 9 or #(4.23,5.67) A1(out,a,b); 10 11 endmodule
1 //半加器 2 module half_add 3 ( 4 input a,b, 5 output cout,sum 6 ); 7 assign sum=a^b; 8 assign cout=a&b; 9 endmodule
1 //8位全加器 2 module adder8 3 ( 4 input [7:0] a,b, 5 input c, 6 output reg [7:0] sum, 7 output reg cout 8 ); 9 always @(a or b or c) 10 begin 11 sum=a^b^c; 12 cout=(a&b)|(a&c)|(b&c); 13 end 14 endmodule
1 //行为描述方式的1位全加器 2 module full_add_2 3 ( 4 input a,b,c, 5 output reg sum,cout 6 ); 7 always @(a or b or c) 8 begin 9 {cout,sum}=a+b+c;//使用位拼接运算符很好诠释了全加器的实质 10 end 11 endmodule
1 //调用门级原件实现1位全加器 2 module full_add 3 ( 4 input a,b,c, 5 output sum,cout 6 ); 7 wire w,y1,y2,y3; 8 and and1(y1,a,b); 9 and and2(y2,a,c); 10 and and3(y3,b,c); 11 or or1(cout,y1,y2,y3); 12 xor xor1(w,a,b); 13 xor xor2(sum,w,c); 14 endmodule
1 //用上例1位全加器构成4位全加器 2 `include "full_add.v" 3 module full_add4 4 ( 5 input [3:0] a,b, 6 input c, 7 output [3:0] sum, 8 output cout 9 ); 10 wire c1,c2,c3; 11 full_add u0(.a(a[0]),.b(b[0]),.c(c),.sum(sum[0]),.cout(c1)); 12 full_add u0(.a(a[1]),.b(b[1]),.c(c1),.sum(sum[1]),.cout(c2)); 13 full_add u0(.a(a[2]),.b(b[2]),.c(c2),.sum(sum[2]),.cout(c3)); 14 full_add u0(.a(a[3]),.b(b[3]),.c(c3),.sum(sum[3]),.cout(cout)); 15 endmodule
1 //2选1多路数据选择器 2 module mux2 3 ( 4 input [1:0] a,b, 5 input sel, 6 output reg [1:0] q 7 ); 8 always @(a or sel) 9 begin 10 if(sel) 11 q=a; 12 else 13 q=b; 14 end 15 endmodule
//两种数据流描述4选1数据选择器 module mux4_1a ( input a,b,c,d, input s0,s1, output y ); assign y=(~s1&~s0&a)|(~s1&s0&b)|(s1&~s0&c)|(s1&s0&d); endmodule
1 module mux4_1b 2 ( 3 input a,b,c,d, 4 input s0,s1, 5 output y 6 ); 7 assign y=s1?(s0?d:c):(s0?b:a); 8 endmodule
1 //模10计数器 2 module count10 3 ( 4 input clk,rst,start, 5 output reg cout, 6 output [3:0] daout 7 ); 8 reg [3:0] cnt; 9 assign daout=cnt; 10 always @(posedge clk or negedge rst)//异步复位 11 begin 12 if(!rst) 13 begin 14 cnt<=0; 15 cout<=0; 16 end 17 else if(start==1) 18 begin 19 if(cnt==10) 20 begin 21 cnt<=0; 22 cout<=1; 23 end 24 else 25 begin 26 cnt<=cnt+1; 27 cout<=0; 28 end 29 end 30 end 31 endmodule
1 //普通8-3编码器 2 module code8_3 3 ( 4 input [7:0] I, 5 output reg [2:0] Q 6 ); 7 always @(I) 8 begin 9 case(I) 10 8‘b00000001:Q=7; 11 8‘b00000010:Q=6; 12 8‘b00000100:Q=5; 13 8‘b00001000:Q=4; 14 8‘b00010000:Q=3; 15 8‘b00100000:Q=2; 16 8‘b01000000:Q=1; 17 8‘b10000000:Q=0; 18 default:Q=3‘bxxx; 19 endcase 20 end 21 endmodule
1 //8-3优先编码器 2 module code_8_3 3 ( 4 input[7:0] I, 5 input s, 6 output reg [2:0] Q, 7 output reg EO,GS 8 ); 9 always @(s or I) 10 begin 11 if(s) begin Q=7;E0=1;GS=1;end 12 else 13 begin 14 if(~I[7]) begin Q=0;EO=1;GS=0;end 15 else if(~I[6]) begin Q=1;EO=1;GS=0;end 16 else if(~I[5]) begin Q=2;EO=1;GS=0;end 17 else if(~I[4]) begin Q=3;EO=1;GS=0;end 18 else if(~I[3]) begin Q=4;EO=1;GS=0;end 19 else if(~I[2]) begin Q=5;EO=1;GS=0;end 20 else if(~I[1]) begin Q=6;EO=1;GS=0;end 21 else if(~I[0]) begin Q=7;EO=1;GS=0;end 22 else begin Q=7;EO=0;GS=1;end 23 end 24 end 25 endmodule
1 //3-8译码器 2 module decode3_8 3 ( 4 input a,b,c,e1,e2,e3, 5 output reg [7:0]Y 6 ); 7 always @(a or b or c or e1 or e2 or e3) 8 begin 9 if((e1==1)&(e2==0)&(e3==0)) 10 case({c,b,a}) 11 0:Y=8‘b11111110; 12 1:Y=8‘b11111101; 13 2:Y=8‘b11111011; 14 3:Y=8‘b11110111; 15 4:Y=8‘b11101111; 16 5:Y=8‘b11011111; 17 6:Y=8‘b10111111; 18 7:Y=8‘b01111111; 19 default:Y=8‘bX; 20 endcase 21 else 22 Y=8‘b11111111; 23 end 24 endmodule
1 //D触发器 2 module dff 3 ( 4 input clk,rst,d, 5 output reg q 6 ); 7 always @(posedge clk) 8 begin 9 if(rst)//同步复位信号 10 q<=0; 11 else 12 q<=d; 13 end 14 endmodule
1 //采用行为描述方式的基本RS触发器（if语句嵌套） 2 module RSff2 3 ( 4 input R,S, 5 output reg Q,QN 6 ); 7 always @(R or S) 8 if({R,S}==2‘b01) begin Q<=0;QN<=1; end 9 else if({R,S}==2‘b10) begin Q<=1;QN<=0; end 10 else if({R,S}==2‘b10) begin Q<=Q;QN<=QN; end 11 else begin Q<=1‘bX;QN<=1‘bX; end 12 endmodule
1 //采用结构描述方式的基本RS触发器（体现逻辑） 2 module RSff1 3 ( 4 input R,S, 5 output reg Q,QN 6 ); 7 nand u1(Q,S,QN), 8 u2(QN,R,Q); 9 endmodule
1 //主从JK触发器 2 module JKff2 3 ( 4 input J,K,CP, 5 output reg Q,QN 6 ); 7 always @(negedge CP) 8 if({J,K}==2‘b00) begin Q<=Q;QN<=QN; end 9 else if({J,K}==2‘b01) begin Q<=0;QN<=1; end 10 else if({J,K}==2‘b10) begin Q<=1;QN<=0; end 11 else if({J,K}==2‘b11) begin Q<=~Q;QN<=~QN; end 12 else begin Q<=1‘bX;QN<=1‘bX; end 13 endmodule
1 //T触发器 2 module tff 3 ( 4 input clk,t, 5 output reg q 6 ); 7 always @(posedeg clk) 8 begin 9 if(t==0) 10 q<=q; 11 else 12 q<=~q; 13 end 14 endmodule
原文：https://www.cnblogs.com/lizlizliang/p/12037387.html