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[Verilog] indexed part-select +:

时间:2020-02-05 22:06:14      阅读:142      评论:0      收藏:0      [点我收藏+]
 

That syntax is called an indexed part-select. The first term is the bit offset and the second term is the width. It allows you to specify a variable for the offset, but the width must be constant.

Example from the SystemVerilog 2012 LRM:

logic [31: 0] a_vect;
logic [0 :31] b_vect;

logic [63: 0] dword;
integer sel;

a_vect[ 0 +: 8] // == a_vect[ 7 : 0]
a_vect[15 -: 8] // == a_vect[15 : 8]
b_vect[ 0 +: 8] // == b_vect[0 : 7]
b_vect[15 -: 8] // == b_vect[8 :15]

dword[8*sel +: 8] // variable part-select with fixed width

[Verilog] indexed part-select +:

原文:https://www.cnblogs.com/pttkvin/p/12262843.html

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