三分频

 1 module Freq_divide
 2 (
 3     input clk,
 4     input rst_n,
 5     output clk_divide
 6  );
 7  
 8 //----------count the posedge---------------------
 9 reg [1:0] cnt_p;
10 reg clk_p;
11 
12 always @ (posedge clk or negedge rst_n) 
13 if(!rst_n) 
14     cnt_p <= 2‘d0;
15 else if(cnt_p == 2‘d2)
16     cnt_p <= 2‘d0;
17 else 
18     cnt_p <= cnt_p + 1‘b1;
19 
20 always @ (posedge clk or negedge rst_n) 
21 if(!rst_n)     
22     clk_p <= 1‘b0;
23 else if((cnt_p == 2‘d1) || (cnt_p == 2‘d2))
24     clk_p <= ~ clk_p;
25 //---------------------------------------------
26 
27 //----------count the negedge------------------
28 reg [2:0] cnt_n;
29 reg clk_n;
30 
31 always @ (negedge clk or negedge rst_n) 
32 if(!rst_n) 
33     cnt_n <= 2‘d0;
34 else if(cnt_n == 2‘d2) 
35     cnt_n <= 2‘d0;
36 else
37     cnt_n <= cnt_n + 1‘b1;
38     
39 always @ (negedge clk or negedge rst_n) 
40 if(!rst_n) 
41     clk_n <= 1‘b0;
42 else if((cnt_n == 2‘d1) || (cnt_n == 2‘d2)) 
43     clk_n <= ~clk_n;
44 //----------------------------------------------
45 
46 assign clk_divide = clk_p | clk_n;
47 
48     
49 endmodule