单端口异步读写

module sp_ram_asy#(parameter DATA_WIDTH=8,ADDRESS_WIDTH=8,RAM_DEEPTH=1<<ADDRESS_WIDTH)(
                cs,
                we,
                address,
                oe,    
                data
                );
    input cs;
    input we;
    input [ADDRESS_WIDTH-1:0]address;
    input oe;
    inout [DATA_WIDTH-1:0]data;
    reg [DATA_WIDTH-1:0]mem[RAM_DEEPTH-1:0];
    reg [DATA_WIDTH-1:0]data_out;
    //synopsys translate_off
    integer i;
    initial begin
        for(i=0;i<RAM_DEEPTH;i=i+1)begin
            mem[i]=8‘h00;
        end
    end
    //synopsys translate_on
    //write
    always@(cs or we or address)
    begin:MEM_WRITE
        if(cs&&we)
            mem[address]=data;
    end
    //read
    always@(cs or we or oe or address)
    begin:MEM_READ
        if(cs&&!we&&oe)
            data_out=mem[address];
    end
    //tri control
    assign data=(cs && (!we) && oe)?data_out:8‘bz;
endmodule 

`timescale 1ns/1ns
module sp_ram_asy_tb();
    reg cs;
    reg we;
    reg [7:0]address;
    reg oe;
    wire [7:0]data;
    reg [7:0]data_in;
    integer i;
    assign data=(cs&&we&&!oe)?data_in:8‘bz;
    sp_ram_asy#(.DATA_WIDTH(8),.ADDRESS_WIDTH(8))sp_ram_asy(
                .cs(cs),
                .we(we),
                .address(address),
                .oe(oe),
                .data(data)
                );
    initial begin
        cs=1‘b0;
        we=1‘b0;
        oe=1‘b0;
        data_in=8‘d0;
        address=8‘d0;
        #20;
        //读初值
        begin
            cs=1‘b1;
            we=1‘b0;
            oe=1‘b1;
        end
        #4;
        for(i=0;i<256;i=i+1)begin
            #4 begin
            address=i;
            end
        end
        #1200;
        //写
        begin
            cs=1‘b1;
            we=1‘b1;
            oe=1‘b0;
        end
        #4;
        for(i=0;i<256;i=i+1)begin
            #4 begin
            data_in=data_in+1;
            address=i;
            end
        end    
        #1200;
        //读
        begin
            cs=1‘b1;
            we=1‘b0;
            oe=1‘b1;
        end
        #4;
        for(i=0;i<256;i=i+1)begin
            #4 begin
                address=i;
            end
        end
        #1200;
        
            cs=1‘b0;
        #100;
        $stop;
    end
endmodule