使用BCD计数器设计时钟

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: connor jiao
// Create Date: 21:42 2020/8/5
// Design Name: 
// Module Name: 
// Function   : 
//用计数器设计一个带am/pm的12小时时钟。该计数器通过一个CLK进行计时，用ena使能信号来驱动时钟的递增。
//reset信号将时钟复位为12：00 AM。 信号pm为0代表AM，为1代表PM。
//hh、mm和ss由两个BCD计数器构成hours(01~12)， minutes(00~59) , second(00~59)。
//Reset信号比enable信号有更高的优先级，即使没有enable信号也可以进行复位操作。 
// Revision 0.01 - File Created
// Additional Comments:
//////////////////////////////////////////////////////////////////////////////////
module top_clk(
                input clk,
                input reset,
                input en,
                output pm,
                output [7:0]hh,//因为用的BCD，最大到9，需要两组
                output [7:0]mm,
                output [7:0]ss
                );
    
    
//============================================================================
//*******************Define parameter and Internal Signals********************
//============================================================================
    reg [7:0]cnt_out1;
    reg [7:0]cnt_out2;
    reg [7:0]cnt_out3;
    
    reg p;
//============================================================================
//********************************Main Code***********************************
//============================================================================
    always@(posedge clk )
    begin
        if(reset)
            cnt_out1<=‘d0;
        else begin
            if(en)
                if(cnt_out1==8‘h59)//注意这里是16进制的5,9哦,这道题的灵魂所在
                    cnt_out1<=‘d0;
                else begin 
                    if(cnt_out1[3:0]==‘d9)
                    begin
                        cnt_out1[3:0]<=‘d0;
                        cnt_out1[7:4]<=cnt_out1+1‘b1;
                    end 
                    else
                        cnt_out1[3:0]<=cnt_out1[3:0]+1‘b1;
                end
            else
                cnt_out1<=‘d0;
        end
    end
    always@(posedge clk )
    begin
        if(reset)
            cnt_out2<=‘d0;
        else begin
            if(en&&cnt_out1==8‘h59)
                if(cnt_out2==8‘h59)//注意这里是16进制的5,9哦
                    cnt_out2<=‘d0;
                else begin 
                    if(cnt_out2[3:0]==‘d9)
                    begin
                        cnt_out2[3:0]<=‘d0;
                        cnt_out2[7:4]<=cnt_out2+1‘b1;
                    end 
                    else
                        cnt_out2[3:0]<=cnt_out2[3:0]+1‘b1;
                end
            else
                cnt_out2<=‘d0;
        end
    end
    always@(posedge clk )
    begin
        if(reset)
            cnt_out3<=‘d0;
        else begin
            if(en&&cnt_out2==8‘h59&&cnt_out1==8‘h59)
                if(cnt_out3==8‘h12)//注意这里是16进制的1,2哦
                    cnt_out3<=‘d0;
                else begin 
                    if(cnt_out3[3:0]==‘d9)
                    begin
                        cnt_out3[3:0]<=‘d0;
                        cnt_out3[7:4]<=cnt_out3+1‘b1;
                    end 
                    else
                        cnt_out3[3:0]<=cnt_out3[3:0]+1‘b1;
                end
            else
                cnt_out3<=‘d0;
        end
    end
    
    always@(posedge clk)
    begin
        if(reset)
            p<=0;
        else if(en&&cnt_out3==8‘h11&&cnt_out2==8‘h59&&cnt_out1==8‘h59)
            p<=~p;
        else
            p<=p;
    end
    assign pm=p;
    assign ss=cnt_out1;
    assign mm=cnt_out2;
    assign hh=cnt_out3;
endmodule