习题8 #第8章 Verilog有限状态机设计-3 #Verilog #Quartus #modelsim

 1 // 8-bit light and 3 shows
 2 //2020-10-13 
 3 // by YongFengXie
 4 module ex8_3(clk,rst_n,lamb);
 5 input clk;
 6 input rst_n;
 7 output reg [7:0] lamb;
 8 
 9 reg [3:0] state;
10 
11 parameter s0=4‘b0000,
12           s1=4‘b0001,
13           s2=4‘b0011,
14           s3=4‘b0010,
15           s4=4‘b0110,
16           s5=4‘b0111,
17           s6=4‘b0101,
18           s7=4‘b0100,
19           s8=4‘b1100,
20           s9=4‘b1101,
21           s10=4‘b1111,
22           s11=4‘b1110;
23 
24 always @(posedge clk or negedge rst_n)
25 begin
26   if(!rst_n)
27     begin
28       state<=s0;
29       lamb<=8‘b0000_0000; // all off
30     end
31   else
32     begin
33       case(state)
34         s0:begin                 // 1 mode
35              state<=s1;
36              lamb<=8‘b0000_0000; // all off
37            end
38         s1:begin
39              state<=s2;
40              lamb<=8‘b1111_1111; // all on
41            end
42         s2:begin                 // 2 mode
43              state<=s3;
44              lamb<=8‘b1000_0000; // 1st on(from left to right)
45            end
46         s3:begin
47              state<=s4;
48              lamb<=8‘b0100_0000; // 2nd on
49            end
50         s4:begin
51              state<=s5;
52              lamb<=8‘b0010_0000; // 3rd on(from left to right)
53            end
54         s5:begin
55              state<=s6;
56              lamb<=8‘b0001_0000; // 4th on
57            end
58         s6:begin
59              state<=s7;
60              lamb<=8‘b0000_1000; // 5th on
61            end
62         s7:begin
63              state<=s8;
64              lamb<=8‘b0000_0100; // 6th on
65            end
66         s8:begin
67              state<=s9;
68              lamb<=8‘b0000_0010; // 7th on
69            end
70         s9:begin
71              state<=s10;
72              lamb<=8‘b0000_0001; // 8th on
73            end
74         s10:begin                // 3 mode
75              state<=s11;
76              lamb<=8‘b0101_0101; // 4 on 4 off
77            end
78         s11:begin
79              state<=s0;
80              lamb<=8‘b1010_1010; // 4 on 4 off
81            end
82         default:begin
83                   state<=s0;
84                   lamb<=8‘b0000_0000; 
85                 end
86       endcase
87     end
88 end
89 
90 endmodule

 1 //ex8_3 testbench
 2 //2020-10-13 
 3 // by YongFengXie
 4 `timescale 1ns/1ns
 5 module ex8_3tb;
 6 reg clk;
 7 reg rst_n;
 8 wire [7:0] lamb;
 9 
10 initial begin
11           clk=1‘b0;
12           rst_n=1‘b0;
13           #40 rst_n=1‘b1;
14           #200 $stop;
15         end
16 
17 always #5 clk=~clk;
18 
19 ex8_3 ub(clk,rst_n,lamb);
20 
21 endmodule