Simultaneous Multithreading: Maximizing On-Chip Parallelism

Time

2020.11.02

Summary

1.introduce several SM models
2.evaluate th performance of those models relative to superscalar and fine-grain multithreading
3.show how to tune the cache hierarchy for SM processors
4.demonstrate the potential for performance and real-estate advantages of SM

Research Objective

Simultaneous Multithreading(SM)

Problem Statement

1.simultaneous multithreading has excellent potential to increase processor utilization,it can add complexity to the design.

2.The objective of SM is to increase processor utilization.

Method(s)

Evaluation

1.To place our evaluation in the context of modern superscalar processors, we simulate a base architecture derived from the 300 MHz Alpha 21164.
为了将我们的评估放在现代超标量处理器的上下文中，我们模拟了一个从300 MHz Alpha 21164派生的基本架构。

Conclusion

Notes

1.The binding between threa and functional unit is completly dynamic.
2.Simultaneous mukithreading combines the multiple-issue-per-instruction features with the latency-hiding ability
3.Multiple instruction issue is limited by instruction dependencies and long-latency operations(Figure 1 can illustrate)
3.1 vertical waste:when the processor issues no instructions in a cycle.
3.2 horizontal waste:when not all issue slots can be filled in a cycle.
3.3 Superscalar execution both introduces horizontal waste and increases the amount of vertical waste.
4.Traditional multithreading hides memory and firnctional unit latencies, attacking vertical waste.
5.Simultaneous multithreading attacks both horizontal and vertical waste.

Professional terms

Words

Sentence

1.evaluate th performance of those models relative to superscalar and fine-grain multithreading
评估这些模型相对于超标量和细粒度多线程的性能
2.To place our evaluation in the context of modern superscalar processors, we simulate a base architecture derived from the 300 MHz Alpha 21164.
为了将我们的评估放在现代超标量处理器的背景下，我们模拟了一个从300 MHz Alpha 21164派生的基本架构。

TimtLine

our SM architectures are extensions of that basic design

Simultaneous Multithreading: Maximizing On-Chip Parallelism

原文：https://www.cnblogs.com/call-me-dasheng/p/13913781.html