module key( clk,sys_rst_n,key_en,key_in);
input clk;
input sys_rst_n;
input key_in;
output key_en;
//这两段代码前面分别进行计数和在计数满产生一个高脉冲信号cnt_full
//20ms计数器
reg cnt_full;
reg [19:0] cnt;
always@(posedge clk or negedge sys_rst_n)
begin
if(!sys_rst_n)
cnt <= 20‘d0;
else if(cnt == 20‘d1000000-1) //20ms/20ns=1000_000
cnt <= 20‘d0;
else
cnt <= cnt + 1‘b1;
end
//计数满信号
always@(posedge clk or negedge sys_rst_n)
begin
if(!sys_rst_n)
cnt_full <= 1‘b0;
else if(cnt == 20‘d1000000-1)
cnt_full <= 1‘b1;
else
cnt_full <= 1‘b0;
end
//这两段代码就是来用实现取前后按键信号的
reg key_in_r;
reg key_in_r_next;
always@(posedge clk or negedge sys_rst_n)
begin
if(!sys_rst_n)
key_in_r_next <= 0;
else if(cnt_full)
key_in_r_next <= key_in;
else
key_in_r_next <= key_in_r_next;
end
always@(posedge clk or negedge sys_rst_n)
begin
if(!sys_rst_n)
key_in_r <= 0;
else
key_in_r <= key_in_r_next;
end
assign key_en = ~key_in_r & (key_in_r_next);
endmodule
原文:https://www.cnblogs.com/zqh1126/p/14406768.html