# HDLbits——Exams/2014 q4b

## 题目要求 Write a top-level Verilog module (named top_module) for the shift register, assuming that n = 4. Instantiate four copies of your MUXDFF subcircuit in your top-level module. Assume that you are going to implement the circuit on the DE2 board.

Connect the R inputs to the SW switches,

• clk to KEY,
• E to KEY,
• L to KEY, and
• w to KEY.
Connect the outputs to the red lights LEDR[3:0].
``````
// Write a top-level Verilog module (named top_module) for the shift register, assuming that n = 4. Instantiate four copies of your MUXDFF subcircuit in your top-level module. Assume that you are going to implement the circuit on the DE2 board.

// Connect the R inputs to the SW switches,
// clk to KEY,
// E to KEY,
// L to KEY, and
// w to KEY.
// Connect the outputs to the red lights LEDR[3:0].

module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
); //

MUXDFF ins3_MUXDFF(.clk(KEY), .R(SW),.E(KEY),.L(KEY),.w(KEY), .Q(LEDR));

MUXDFF ins2_MUXDFF(.clk(KEY),.R(SW),.E(KEY),.L(KEY),.w(LEDR),.Q(LEDR));

MUXDFF ins1_MUXDFF(.clk(KEY),.R(SW),.E(KEY),.L(KEY),.w(LEDR),.Q(LEDR));

MUXDFF ins0_MUXDFF(.clk(KEY),.R(SW),.E(KEY),.L(KEY),.w(LEDR),.Q(LEDR));

endmodule

module MUXDFF (
input clk,
input w, R, E, L,
output reg Q
);

wire D_i;
assign D_i = L?R:(E?w:Q);
always @(posedge clk) begin
Q <= D_i;
end

endmodule
``````

RTL原理图 HDLbits——Exams/2014 q4b

(0)
(0)