/***************************************************
/ Blocking and Nonblocking circuit and Simulation
/ Using level sensitive event
/ Programing by seongki
***************************************************/
module Blocking (in_A,in_B,in_C,in_D,out_A,out_B,out_C,out_D);
input [3:0] in_A,in_B,in_C,in_D;
output [3:0] out_A,out_B,out_C,out_D;
reg [3:0] out_A,out_B,out_C,out_D;
always@(in_A or in_B or in_C or in_D)
begin
out_C=in_C; out_B=in_B; out_A=in_A; out_D=in_D;
out_A=out_D; out_B=out_A; out_C=out_B; out_D=out_D;
end
endmodule
// testbench
`timescale 1ns/1ns
module tb_Blocking;
reg [3:0] in_A,in_B,in_C,in_D;
wire [3:0] out_A,out_B,out_C,out_D;
Blocking test1(in_A,in_B,in_C,in_D,out_A,out_B,out_C,out_D);
initial
begin
in_A = 5;
in_B = 3;
in_C = 10;
in_D = 2; #250
$stop;
end
endmodule
/****************************************************************/
module NonBlocking (in_A,in_B,in_C,in_D,out_A,out_B,out_C,out_D);
input [3:0] in_A,in_B,in_C,in_D;
output [3:0] out_A,out_B,out_C,out_D;
reg [3:0] out_A,out_B,out_C,out_D;
always@(in_A or in_B or in_C or in_D)
begin
out_C=in_C; out_B=in_B; out_A=in_A; out_D=in_D;
out_A<=out_D; out_B<=out_A; out_C<=out_B; out_D<=out_D;
end
endmodule
// testbench
`timescale 1ns/1ns
module tb_nonBlocking;
reg [3:0] in_A,in_B,in_C,in_D;
wire [3:0] out_A,out_B,out_C,out_D;
NonBlocking test2(in_A,in_B,in_C,in_D,out_A,out_B,out_C,out_D);
initial
begin
in_A = 5;
in_B = 3;
in_C = 10;
in_D = 2; #250
$stop;
end
endmodule
PS: Blocking & Nonblocking? ?? ??.
??? edge sensitive event? ?????.
原文：http://www.cnblogs.com/capark/p/4004464.html