Solution ID: fb83262
Last Modified: May 17, 2013
Product Category: Intellectual Property
Product Area: Comm, Interface & Peripherals
Product Sub-area: IP Spec and Protocol
Version Found In: v12.1
Version Fixed In: v13.0
Title
Description
The RapidIO II MegaCore Function User Guide lists the instructions to simulate the demonstration testbench included with the IP core using the ModelSim simulator. However, in variations that include an I/O Logical layer Master module or an I/O Logical layer Slave module, ModelSim simulation fails using these instructions.
The error occurs during loading, and displays as "Fatal: Error occurred in protected context."
Workaround / Fix
To avoid this issue, for variations that include an I/O Logical layer Master module or an I/O Logical layer Slave module, replace the ld command with the ld_debug command in the command sequence listed in the "Simulating with the ModelSim Simulator" section in the Getting Started chapter of the RapidIO II MegaCore Function User Guide.
This issue is fixed in version 13.0 of the RapidIO II MegaCore function.
ModelSim Simulation of RapidIO II IP Core Demonstration Testbench May Require ld_debug Command
原文：http://www.cnblogs.com/fpga/p/4041431.html