verilog中的for循环问题

module mult_for(outcome,a,b);
parameter SIZE=8;
input[SIZE:1] a,b;
output reg[2*SIZE:1] outcome;
integer i;
always @(a or b)
        begin outcome<=0;
        for(i=0,i<=SIZE;i++)
        if(b[i]) outcome<=outcome+(a<<(i-1));
        end
endmodule

为何总出现如下错误;

Error (10170): Verilog HDL syntax error at mult_for.v(8) near text "<=";  expecting "="
Error (10170): Verilog HDL syntax error at mult_for.v(8) near text "+";  expecting "<=", or "="

verilog中的for循环问题

原文：http://www.cnblogs.com/shaogang/p/4197365.html