状态机写法

 1 module FSM(clk,rst,in,out);
 2 02 input clk,rst;
 3 03 input [7:0] in;
 4 04 output [7:0] out;
 5 05 
 6 06 parameter [1:0] //synopsys enum code
 7 07 START = 2‘d0,
 8 08 SA = 1,
 9 09 SB = 2,
10 10 SC = 3;
11 11 
12 12 reg [1:0] CS,NS;
13 13 reg [7:0] tmp_out,out;
14 14 
15 15 // state transfer
16 16 always @ (posedge clk or negedge rst)
17 17 begin
18 18 if (!rst) CS <= #1 START;
19 19 else      CS <= #1 NS;
20 20 end
21 21 
22 22 // state transfer discipline
23 23 always @ (in or CS)
24 24 begin
25 25     NS = START;
26 26     case (CS)
27 27        START: case (in[7:6])
28 28                        2‘b11: NS = SA;
29 29                        2‘b00: NS = SC;
30 30                        default: NS = START;
31 31                        endcase
32 32        SA: if(in == 8‘h3c) NS = SB;
33 33        SB: begin
34 34                 if (in == 8‘h88) NS = SC;
35 35                 else             NS = START;
36 36                 end
37 37        SC: case(1‘b1) //synopsys parallel_case full_case
38 38                 (in == 8‘d0): NS = SA;
39 39                 (8‘d0 < in && in < 8‘d38): NS = START;
40 40                 (in > 8‘d37): NS = SB;
41 41                   endcase
42 42        endcase
43 43 end
44 44 
45 45 // temp out
46 46 always @ (CS)
47 47 begin
48 48     tmp_out = 8‘bX;
49 49     case (CS)
50 50        START: tmp_out = 8‘h00;
51 51        SA:   tmp_out = 8‘h08;
52 52        SB:   tmp_out = 8‘h18;
53 53        SC:   tmp_out = 8‘h28;
54 54     endcase
55 55 end
56 56 
57 57 // reg out
58 58 always @ (posedge clk or negedge rst)
59 59 begin
60 60     if (!rst) out <= #1 8‘b0;
61 61     else     out <= #1 tmp_out;
62 62 end
63 63 
64 64 endmodule