verilog阻塞与非阻塞的初步理解

module blocking(clk,a,b,c);
  input[3:0] a;
  input clk;
  output[3:0] b,c;
reg[3:0] b,c;
always @(posedge clk)
    begin
      b=a;
      c=b;
            $display("blocking:a=%d,b=%d,c=%d.",a,b,c);
    end
endmodule

module non_blocking(clk,a,b,c);
  input[3:0] a;
  input clk;
  output[3:0] b,c;
reg[3:0] b,c;
always @(posedge clk)
    begin
      b<=a;
      c<=b;
      $display("non_blocking:a=%d,b=%d,c=%d.",a,b,c);
    end
endmodule

`timescale 1ns/100ps
`include"blocking.v"
`include"non_blocking.v"

module top_blocking;
wire[3:0] b1,c1,b2,c2;
reg[3:0] a;
reg clk;


initial 
  begin
    clk=0;
    forever #50 clk=~clk;
  end
  
initial
begin
  a=4‘h3;
  $display("________________");
  #100 a=4‘d7;
  $display("________________");
  #100 a=4‘d15;
    $display("________________");
  #100 a=4‘d10;
    $display("________________");
  #100 a=4‘d2;
    $display("________________");
  #100 $display("________________");
  $stop;
end
non_blocking non_bloking1(clk,a,b2,c2);
blocking blocking1(clk,a,b1,c1);
endmodule